The modern “electronic warfare” environment often includes a plethora of radar signals of varying frequency and bandwidth. Continuous digital sampling of this wideband signal environment to identify and characterize radar pulse trains on the received radar signals inevitably requires a high data sampling rate. This results in enormous amounts of data to be buffered and processed. Using current receiver architectures, the processing of this large amount of data generally requires an extremely complex, costly processor. On the other hand, to keep up in real time with dense electronic warfare environments when standard processor architectures are used, this large amount of data reduces processor performance and tends to limit the types of processing algorithms that can be employed to detect and identify targets.
With regard to processing algorithms, novel methods for characterizing a radar pulse to identify a radar emitter have been recently developed. Typically, in these methods specific data parameters can be extracted from the incoming radar signal and used to identify and classify a non-stationary signal emitter. More specifically, this process includes the step of deinterleaving the input signal into its constituent pulse trains using either an “identify-and-subtract” technique or a Hilbert-Huang transform (HHT). After the deinterleaving process is complete, a Hilbert transform is applied to a selected pulse train to characterize a single radar pulse from the pulse train.
The characterization described above typically includes estimating pulse modulation, bandwidth, pulsewidth and amplitude. Once the pulse, and hence the input signal, is characterized, the characterization data is used to identify and classify the signal emitter. Thus, in addition to decreasing overall processor load, it is also highly desirable to match the radar receiver architecture to the specific computational algorithms that will be used to identify and classify emitters/targets. In this manner, the receiver can be configured to extract only the selected data required by the specific computational algorithm.
Another factor that must be considered when designing a receiver architecture is throughput speed. In this regard, it is known that hardware circuits can perform some data computations much quicker than software equipped processors. For example, in some cases, dedicated hardware circuits can perform a computation in as little as two or three clock cycles, whereas the same computation may require a time duration of several orders of magnitude greater when performed by a software equipped processor.
In light of the above, it is an object of the present invention to provide a radar receiver architecture which reduces processor load by digitizing only a selected portion of an incoming wideband signal. Still another object of the present invention is to provide a radar receiver architecture that can be selectively matched to a specific computational algorithm. Yet another object of the present invention is to provide a radar receiver architecture for receiving and analyzing wideband radar signals that is relatively efficient, is relatively simple to use, and is comparatively cost effective.